1. Field of the Invention
The present invention relates to the manufacturing methods of a well region and a channel stopper in a CMOS integrated circuit.
2. Description of the Prior Art
It is known that the performance of a CMOS integrated circuit can be enhanced by reducing the gate length of the CMOS integrated circuit. In that case, it is necessary in general to set the impurity concentration of the wells and a semiconductor substrate at a high level in order to control the short channel effect.
In a P-channel MOS transistor of a CMOS integrated circuit using N-type silicon substrate, there is generally employed an N-type polycrystalline silicon film as a gate electrode material. For this reason, a P-type layer is formed on the surface of an N well by ion implanting P-type impurity ions. This structure is referred to as being of buried channel type.
It should be noted that a straight forward increase of the impurity concentration of the N wells makes the difference from the impurity concentration of the P-type layer formed on the N-well surface small, impairing the controllability of the threshold voltage. Moreover, in the channel region of the P-channel MOS transistor in the N well, the P-type and the N-type impurity concentrations are high and, therefore, the hole mobility is reduced due to scattering, so that the current driving ability of the P-channel MOS transistor will be reduced.
In order to circumvent the above-mentioned difficulties there is known a fabrication method in which the ion implantation for the N-well formation is performed after the formation of the field oxide film and the heat treatment is moderated to suppress the impurity concentration rise in the vicinity of the N-well surface layer. In this case, it is not possible to simultaneously form the N wells and the N-type channel stoppers by the implantation of ions with energy of 100 to 200 keV because the field oxide film requires a thickness of 500 to 800 nm. On the other hand, implantation of ions with energy not less than several hundred kiloelectron volts will permit the simultaneous formation of the N wells and the N-type channel stoppers. However, this is not desirable since the impurity concentration of the N-type channel stoppers will become lower compared with the impurity concentration of the N wells.
For the above-mentioned reasons, the conventional N-type channel stoppers are formed as described in the following.
First, an SiO.sub.2 film is formed on an N-type silicon substrate. Then, boron ions are implanted into a region which is to become the element formation region of an N-channel MOS transistor and a region which is to become the element isolation region of an N-channel MOS transistor, by using a first photoresist film as the mask. The ion implantation is performed for the purpose of forming P wells.
Next, after removal of the first photoresist film, an Si.sub.3 N.sub.4 film is deposited all over the top surface of the N-type silicon substrate. With a second photoresist film as the mask, the Si.sub.3 N.sub.4 film on the region which is to become the element isolation region of the N-channel MOS transistor and on the region which is to become the element isolation region of a P-channel MOS transistor is removed by etching. The Si.sub.3 N.sub.4 film on the region which is to become the element formation region of the N-channel MOS transistor and on the region which is to become an element formation region of the P-channel MOS transistor stays there without being removed. Further, in the portion where the N-channel MOS transistor and the P-channel MOS transistor are formed adjacent with each other, the regions that are to become the element isolation regions of the N-channel and the P-channel MOS transistors are situated adjacent with each other.
Next, a third photoresist film is formed, without removing the second photoresist film, on the second photoresist film and on the region which is to become the element isolation region of the P-channel MOS transistor. Boron ions are implanted into the regions which are to become the element isolation region of the N-channel MOS transistors, using the second and the third photoresist films as the mask. This ion implantation is performed to form P-type channel stoppers in the element isolation regions of the N-channel MOS transistors.
Then, the second photoresist film and the third photoresist film are removed.
Following that, a fourth photoresist film is formed ideally on the region other than that which is to become the element isolation region of the P-channel MOS transistor. In other words, the fourth photoresist film is formed on the Si.sub.3 N.sub.4 film on the regions that are to become the element formation regions of the N-channel MOS transistor and the P-channel MOS transistor, and on the region that is to become the element isolation region of the N-channel MOS transistor. Succeeding the above, phosphorus ions are implanted ideally into the region that is to become the element isolation region of the P-channel MOS transistor, using the fourth photoresist film as the mask. The ion implantation is performed for the purpose of forming an N-type channel stopper in the region.
Next, the fourth photoresist film is removed. A field oxide film is selectively formed in the regions that are to become the element isolation regions of the P-channel and the N-channel MOS transistors, with the Si.sub.3 N.sub.4 film as the mask. The oxidation is carried out in the oxidizing atmosphere of H.sub.2 and O.sub.2. Simultaneous with the formation of the field oxide film, there are formed P wells in the region which is to become the element isolation region of the N-channel MOS transistor as well as in the region which is to become the element isolation region of the N-channel MOS transistor; the element isolation region, for the N-channel MOS transistor consisting of the field oxide film and the P-type channel stopper, is formed in the region which is to become the element isolation region of the N-channel MOS transistor, and the element isolation region, for the P-channel MOS transistor consisting of the field oxide film and the N-type channel stopper, is formed in the region which is to become the element isolation region of the P-channel MOS transistor.
In the above, the depth in the vertical direction of the diffused layer of the P-type channel stopper is 0.7 to 1.0 .mu.m. Further, the depth in the vertical direction of the diffused layer of the N-type channel stopper is 0.19 to 0.24 .mu.m, and the surface impurity concentration of the N-type channel stopper is (0.56 to 1.0).times.17.sup.17 cm.sup.-3. Because of this, the sum of the horizontal direction of the P-type channel stopper (or the P well) and the diffused layer of the N-type channel stopper becomes layer than the alignment accuracy. Therefore, no slit will be formed between the N-type channel stopper and the P-type channel stopper (or the P well).
Then, the Si.sub.3 N.sub.4 film is removed. Next, a fifth photoresist film is formed on the P wells. Subsequently, with the fifth photoresist film as the mask, phosphorus ions are implanted. At this time, ions are implanted into the region planned for the element formation region of the P-channel MOS transistor. However, ions will not be implanted into the N-type channel stopper because of the large thickness of the field oxide film.
Next, after removal of the fifth photoresist film, a heat treatment is subjected to the above-obtained substrate. As a result of this treatment, the phosphorus ions implanted into the region planned for the element formation region of the P-channel MOS transistor are activated, and forms an N well in the region. The depth in the vertical direction of the N-well diffused layer is 0.41 to 0.43 .mu.m, and the surface impurity concentration of the N well is (0.22 to 0.4).times.10.sup.17 cm.sup.-3. It is to be noted that there is practically no horizontal spread of the N-well diffused layer.
In the manufacturing method of the N well described in the above, the N well itself is formed in self-aligning manner with respect to the field oxide film, but the N-type channel stopper will not be formed in self-aligning manner with respect to the field oxide film. Taking into account even the horizontal spread of the diffused layer of the N-type channel stopper which is smaller than the alignment accuracy, it will be understood that the N well and the N-type channel stopper will not necessarily be brought into contact. The cause of the variability in this situation resides in the presence of alignment deviation of the fourth photoresist film, when the fourth photoresist film is deviated toward the N-well side at one end part of the N well, the impurity concentration of the N well at this end part will become high. At the opposite end part of the N well which faces the end part, the fourth photoresist film is deviated to the side to be away from the N well, so that either the impurity concentration of the N-type channel stopper at this portion becomes lower or the N-type channel stopper will become off-set with respect to the N well.
Due to the circumstances described above, there will arise the following problems. Namely, when the impurity concentration of the N well becomes high at one end part of the N well, the threshold voltage of the P-channel MOS transistor becomes locally high, the junction breakdown voltage of a P.sup.+ diffused layer is reduced and the junction capacitance of the P.sup.+ diffused layer is increased. On the other hand, when the impurity concentration of the N-type channel stopper becomes low at an end part of the N well or the N-type channel stopper is off-set with respect to the N well, the threshold voltage of the P-channel parasitic MOS transistor at this part becomes low and the junction capacitance of the P.sup.+ diffused layer becomes low. It is to be noted that when the above-mentioned changes take place, one situation alone will not occur but both of them occur simultaneously.
It is to be noted that the aforementioned problems exist also in the case of Bi-CMOS integrated circuit.